FIG. 1 illustrates a cross sectional view of a conventional multi-stack chip size package (CSP).
Referring to FIG. 1, a first chip (or die) 21 is adhered on a substrate 11, e.g., a printed circuit board, with an epoxy and a second die 31 is stacked on the first chip 21 with the epoxy. Bonding pads on the first and the second chip 21 and 31 are electrically connected with terminals on the printed circuit board 11 by conductive wires 51. A resin, e.g., an epoxy molding compound (EMC) 41 is used to mold the first and the second chip 21 and 31, and the electrical connection between the whole package and another printed circuit board can be achieved by a ball grid array using solder balls 61.
The drawback of this conventional multi-stack chip size packaged device is that a thickness thereof is to be enlarged, e.g., about 1.4 mm, because of the molding material of the multi-stack CSP, i.e., the resin, to thereby require a long conductive wires 51, i.e., a long signal transmission path. Therefore, the characteristics of the multi-stack chip size packaged device are deteriorated and the applicability thereof is also reduced. In addition, heat dissipation thereof is not effective.